ADSP-214xx SHARC Processor Hardware Reference 15-23
Serial Peripheral Interface Ports
DMA Chaining
The serial peripheral interfaces support both single and chained DMA.
However, unlike the serial ports, programs cannot insert a TCB in an
active chain. For more information, see “SPI TCB” on page 2-14.
Configuring and starting chained DMA transfers over the SPI port is the
same as for the serial ports, with one exception. Contrary to SPORT
DMA chaining, (where the first DMA in the chain is configured by the
first TCB), for SPI DMA chaining, the first DMA is not initialized by a
TCB. Instead, the first DMA in the chain must be loaded into the SPI
parameter registers (
IISPI, IMSPI, CSPI, IISPIB, IMSPIB, CSPIB), and the
chain pointer registers (CPSPI, CPSPIB) point to a TCB that describes the
second DMA in the sequence.
Writing an address to the CPSPIx, registers does not begin a
chained DMA sequence unless the IISPI, IMSPI, CSPI, IISPIB,
IMSPIB, and CSPIB registers are initialized, SPI DMA is enabled,
the SPI port is enabled, and SPI DMA chaining is enabled.
DMA Transfer Count
When the SPI is configured for receive/transmit DMA, the number of
words configured in the DMA count register should match the actual data
transmitted. When the SPI DMA is used, the internal DMA request is
generated for a DMA count of four. In case the count is less than four, one
DMA request is generated for all the bytes.
For example, when a DMA count of 16 is programmed, four DMA
requests are generated (that is, four groups of four). For a DMA count of
18, five DMA requests are generated (four groups of four and one group
of two). In case the SPI DMA is programmed with a value more than the
actual data transmitted, some bytes may not be received by the SPI DMA
due to the condition for generating the DMA request.
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