Data Transfers
15-22 ADSP-214xx SHARC Processor Hardware Reference
When enabled as a master, the DMA engine transmits or receives data as
follows:
• If the SPI system is configured for transmitting, the DMA engine
reads data from memory into the DMA FIFO. Data from the
DMA FIFO is loaded into the
TXSPIx buffer and then into the
transmit shift register. This initiates the transfer on the SPI port.
• If configured to receive, data from the RXSPIx buffer is automati-
cally loaded into the DMA FIFO. Then the DMA engine reads
data from the DMA FIFO and writes to memory. Finally, the SPI
initiates the receive transfer. The SPI generates the programmed
signal pulses on SPICLK and the data is shifted out of MOSI and in
from MISO simultaneously. The SPI continues sending or receiving
words until the SPI DMA word count register transitions from 1 to
0.
Do not write to the TXSPIx buffer during an active SPI transmit
DMA operation because DMA data will be overwritten. Similarly,
do not read from the RXSPIx buffer during active SPI DMA receive
operations. DMA Interrupts are generated based on DMA events
and are configured in the SPIDMACx registers. In order for a
transmit DMA operation to begin, the transmit buffer (TXSPIx)
must initially be empty (TXS = 0). While this is normally the case,
this means that the TXSPIx buffer should not be used for any pur-
pose other than SPI transfers. Writing to the TXSPIx buffer via the
software sets the
TXS bit.
For receive master DMA the SPICLK stops only when the RXSPI
buffer and DMA FIFO are full (even if the DMA count is already
zero). Therefore,
SPICLK runs for an additional five word transfers
filling junk data in the
RXSPIx buffer and DMA FIFO. The FIFOs
must be flushed before a new DMA is initiated.
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