Functional Description
10-16 ADSP-214xx SHARC Processor Hardware Reference
When the SPORT is configured as a receiver (
SPTRAN = 0), the receive buf-
fers are activated. The receive buffers act like a three-location FIFO
because they have two data registers plus an input shift register.
Frame Sync
The following sections provide information on frame syncs which applies
to the SPORTs in all operating modes. For mode specific frame sync
information, see “Operation Modes” on page 10-21.
Sampling Edge
Data and frame syncs can be sampled on the rising or falling edges of the
serial port clock signals. The CKRE bit of the SPCTLx control registers selects
the sampling edge. For sampling receive data and frame syncs, setting CKRE
to 1 in the SPCTLx register selects the rising edge of SPORTx_CLK. When
CKRE is cleared (=0), the processor selects the falling edge of SPORTx_CLK
for sampling receive data and frame syncs.
Note that transmit data and frame sync signals change their state on the
clock edge that is not selected. For example, the transmit and receive func-
tions of any two serial ports connected together should always select the
same value for CKRE so internally-generated signals are driven on one edge
and received signals are sampled on the opposite edge.
Frame Sync and Data Sampling
The information contained in this section is generic to the SPORTs in any
operating mode. Additional information about frame syncs and data sam-
pling that applies to a specific operating mode can be found in “Operation
Modes” on page 10-21.
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