ADSP-214xx SHARC Processor Hardware Reference 21-11
Two Wire Interface Controller
The TWI controller’s special-case start and stop conditions include:
• TWI controller addressed as a slave-receiver
If the master asserts a stop condition during the data phase of a
transfer, the TWI controller concludes the transfer (
TWISCOMP).
• TWI controller addressed as a slave-transmitter
If the master asserts a stop condition during the data phase of a
transfer, the TWI controller concludes the transfer (TWISCOMP) and
indicates a slave transfer error (TWISERR).
• TWI controller as a master-transmitter or master-receiver
If the stop bit is set during an active master transfer, the TWI con-
troller issues a stop condition as soon as possible to avoid any error
conditions (as if data transfer count had been reached).
Slave Mode Addressing
With the appropriate selection of 7-bit addressing using the TWISLEN bit,
the corresponding number of address bits (SADDR) are referenced during
the address phase of a transfer.
Master Mode Addressing
Whether enabled as a master-transmitter or master-receiver with 7-bit
addressing using the
TWIMLEN bit, the TWI master performs all addressing
and data transfers as required. This includes generating the repeated start
condition, re-transmission of the 7-bits of the first address byte, and
acknowledgement and generation of a new transfer direction change (indi-
cated by the TWIMLEN bit).
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