Phase-Locked Loop (PLL)
22-4 ADSP-214xx SHARC Processor Hardware Reference
PLL Multiplier
The PLL multiplier is controlled by hardware or software and based on
the PLL multiplier settings below.
• Hardware—through the clock configuration pins (CLK_CFG1–0)
• Software—the hardware settings are overridden through the
PLLM
bits
PLLM Hardware Control
On power-up, the
CLK_CFG1–0 pins are used to select core to CLKIN ratios
which cannot be changed during runtime. After booting however, numer-
ous other ratios (slowing or speeding up the clock) can be selected through
software control.
For information on the internal clock to CLKIN frequency ratios supported
by the various processors, see the product specific data sheet.
PLLM Software Control
Programs control the PLL through the PMCTL register. The PLL multiplier
(PLLM) bits can be configured to set a multiplier range of 0 to 63. This
allows the PLL to be programmed dynamically in software to achieve a
higher or slower core instruction rate depending on a particular system’s
requirements.
The reset value of the PLLM bits is derived from the CLK_CFG1–0 pin multi-
ply ratio settings. This value can be reprogrammed in the boot kernel to
take effect immediately after start- up.
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