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Differences from Previous Processors

1-6 ADSP-214xx SHARC Processor Hardware Reference

I/O Architecture Enhancements

The I/O processor provides much greater throughput than the

ADSP-2116x processors. This architecture incorporates two independent

DMA buses versus the previous SHARC DMA controllers:

• one peripheral DMA bus (IOD0)

• one external port DMA bus (IOD1)

This allows to operate all external port DMA accesses independently from

the peripheral buses since up to four internal memory blocks are address-

able without any bus conflicts.

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Contents3
Preface61
- Purpose of This Manual61
- Intended Audience61
- Manual Contents62
- What’s New in This Manual65
- Technical or Customer Support66
- Supported Processors67
- Product Information68
- Notation Conventions70
1 Introduction73
- Design Advantages73
  - SHARC Family Product Offerings74
- Processor Architectural Overview74
  - Processor Core74
  - I/O Peripherals75
- Development Tools77
- Differences from Previous Processors77
  - I/O Architecture Enhancements78
2 I/O Processor79
- Features80
- Register Overview81
- DMA Channel Registers81
- TCB Storage91
- Clocking100
- Functional Description100
- Operating Modes108
- Interrupts123
- Debug Features127
  - Emulation Considerations127
- Effect Latency127
- Programming Model128
  - General Procedure for Configuring DMA129
3 External Port131
- Features132
- Pin Descriptions133
  - Pin Multiplexing133
- Register Overview133
- Clocking AMI/SDRAM135
- Clocking AMI/DDR2136
- External Port Arbitration137
- Functional Description137
  - Operating Mode140
    - Arbitration Freezing140
- Asynchronous Memory Interface140
- SDRAM Controller (ADSP-2147x/ADSP-2148x)147
- DDR2 DRAM Controller (ADSP-2146x)176
- Data Transfer214
- External Port DMA230
- Interrupts244
- External Port Throughput246
- Effect Latency250
  - Write Effect Latency251
- Programming Models251
4 Link Ports—ADSP-2146x265
- Features266
- Pin Descriptions267
- Register Overview267
- Clocking268
- Functional Description268
- Data Transfer277
- Interrupts280
- Debug Features285
  - Shadow Register285
  - Buffer Hang Disable (BHD)286
- Effect Latency286
  - Write Effect Latency286
  - Link Port Effect Latency286
- Programming Model286
5 Memory-to-Memory Port DMA291
- Features292
- Register Overview292
- Clocking292
- Functional Description293
- Data Transfer Types293
  - Data Buffer293
  - DMA Transfer294
- Interrupts294
- MTM Throughput295
- Effect Latency295
  - Write Effect Latency295
  - MTM Effect Latency295
- Programming Model295
6 FFT/FIR/IIR Hardware Modules297
- FFT Accelerator299
- FIR Accelerator324
- IIR Accelerator351
7 Pulse Width Modulation369
- Features370
- Pin Descriptions372
  - Multiplexing Scheme372
- SRU Programming373
- Register Overview373
- Clocking374
- Functional Description374
- Operation Modes386
- Interrupts393
- Debug Features395
  - Status Debug Register395
  - Emulation Considerations395
- Effect Latency395
  - Write Effect Latency395
  - PWM Effect Latency395
8 Media Local Bus397
- Features399
- Pin Descriptions399
- Register Overview400
  - Device Configuration and Status Registers400
  - Channel Configuration Registers400
- Clocking401
- Functional Description401
- Operating Modes403
  - Streaming Channel Frame Synchronization403
  - Big-Endian and Little-Endian Mode404
- Data Transfer404
  - Core Driven Data Transfer404
    - I/O Local Channel Buffering404
  - DMA406
    - Ping-Pong DMA407
    - Circular Buffer DMA409
- Interrupts410
  - Interrupt Source411
  - Servicing Interrupts411
- Debug Features411
  - Loop-Back Test Mode412
- Programming Model412
  - I/O Interrupt Mode412
  - DMA Modes413
9 Digital Application/Digital Peripheral Interfaces415
- Features416
- Register Overview417
- Clocking418
- Functional Description418
- DAI Default Routing442
- DPI Default Routing445
- Interrupts446
- Debug Features454
- Effect Latency456
  - Write Effect Latency456
  - Signal Routing Unit Effect Latency456
- Programming Model456
  - DAI Example System457
10 Serial Ports459
- Features460
- Pin Descriptions462
- SRU Programming463
  - SRU SPORT Receive Master464
  - SRU SPORT Signal Integrity464
- Register Overview465
- Clocking466
- Functional Description468
- Operation Modes479
- Data Transfers497
- Interrupts507
- Debug Features511
  - SPORT Loopback512
    - LoopBack Routing512
  - Buffer Hang Disable (BHD)512
- Effect Latency512
  - Write Effect Latency513
  - SPORT Effect Latency513
- Programming Model513
11 Input Data Port521
- Features522
- Pin Descriptions523
- SRU Programming525
- Register Overview525
- Clocking526
- Functional Description526
- Operating Modes528
- Data Transfer534
- Interrupts543
- Debug Features545
- Effect Latency546
  - Write Effect Latency546
  - IDP Effect Latency546
- Programming Model546
12 Asynchronous Sample Rate Converter553
- Features554
- Pin Descriptions555
- SRU Programming555
- Register Overview556
- Clocking557
- Functional Description557
  - Serial Data Ports561
- Operating Modes561
- Interrupts568
- Debug Features569
- Effect Latency569
  - Write Effect Latency569
  - SRC Effect Latency570
13 Sony/Philips Digital Interface571
- Features572
- Pin Descriptions573
- SRU Programming574
- Register Overview576
- Clocking577
- S/PDIF Transmitter577
  - Functional Description577
    - Input Data Format579
  - Operating Modes581
- S/PDIF Receiver583
  - Functional Description583
  - Operating Modes586
    - Compressed or Non-linear Audio Data586
      - Emphasized Audio Data587
      - Single-Channel Double-Frequency Mode588
    - Clock Recovery Modes588
      - Digital On-Chip PLL588
      - External Analog PLL589
- Interrupts589
- Debug Features591
  - Loop Back Routing591
- Effect Latency591
  - Write Effect Latency591
- Programming Model591
14 Precision Clock Generator595
- Features596
- Pin Descriptions597
- SRU Programming598
- Register Overview599
- Clocking599
- Functional Description600
  - Serial Clock600
  - Frame Sync601
- Operating Modes605
- Effect Latency613
  - Write Effect Latency613
  - PCG Effect Latency613
- Programming Model614
  - Frame Sync Phase Setting614
  - External Event Trigger614
- Debug Features615
15 Serial Peripheral Interface Ports617
- Features618
- Pin Descriptions619
- SRU Programming620
- Register Overview621
- Clocking622
  - Choosing the Pin Enable for the SPI Clock623
- Functional Description624
- Operating Modes628
- Data Transfers634
- Interrupts640
  - Interrupt Sources640
  - Multi Master Error642
- Debug Features643
  - Shadow Receive Buffers643
  - Internal Loopback Mode644
    - Loop Back Routing644
- Effect Latency644
  - Write Effect Latency645
  - SPI Effect Latency645
- Programming Model645
16 Peripheral Timers657
- Features658
- Pin Descriptions659
- SRU Programming659
- Register Overview660
  - Read-Modify-Write661
- Clocking661
- Functional Description661
- Operating Modes663
- Interrupts673
  - Sources673
  - Watchdog Functionality675
- Debug Features675
  - Loopback Routing675
  - Loopback Routing675
- Effect Latency675
  - Write Effect Latency676
  - Peripheral Timers Effect Latency676
- Programming Model677
17 Shift Register – ADSP-2147x681
- Features682
- Pin Descriptions683
- SRU Programming683
- Register Overview684
- Clocking684
- Functional Description685
- Operating Modes686
  - Serial Data Output686
  - Parallel Data Output687
- Effect Latency688
  - Write Effect Latency688
  - Shift Register Effect Latency688
- Programming Model688
18 Real-Time Clock— ADSP-2147x689
- Features690
- Pin Descriptions691
- Clocking691
- Register Overview691
- Functional Description692
- Interrupts698
19 WatchDog Timer – ADSP-2147x705
- Features706
- Pin Descriptions707
- Register Overview707
- Clocking708
- Functional Description708
- Operating Mode710
  - Trip Count710
- Debug Features711
  - Emulation Considerations711
- Effect Latency711
  - Write Effect Latency711
  - Watchdog Timers Effect Latency711
- Programming Model711
20 UART Port Controller715
- Features716
- SRU Programming717
- Register Overview717
- Clocking718
- Functional Description719
  - Serial Communication721
- Operating Modes722
  - Data Packing722
  - 9-Bit Transmission Mode722
    - Packed Mode723
- Data Transfer Types724
- Interrupts728
- Debug Features734
- Effect Latency734
  - Write Effect Latency735
  - UART Effect Latency735
- Programming Model735
21 Two Wire Interface Controller739
- Features740
- Pin Descriptions741
- SRU Programming742
- Clocking742
- Register Overview743
- Functional Description744
- Data Transfer750
  - Data Buffers750
- Operating Modes752
  - General Call Addressing752
  - Fast Mode753
- Interrupts753
  - Interrupt Routing754
    - DPI754
    - TWI754
  - Interrupt Sources755
- Debug Features756
  - Buffer Hang Disable756
  - Loop Back Routing756
- Effect Latency757
  - Write Effect Latency757
  - TWI Effect Latency757
- Programming Model757
- Electrical Specifications764
22 Power Management765
- Features765
- Register Overview765
- Phase-Locked Loop (PLL)766
- Operating Modes771
- Power-Up Sequence772
  - PLL Start-Up773
- Power Management774
- Programming Models777
23 System Design783
- Features783
- Pin Descriptions784
- Register Overview784
- Processor Reset785
- Processor Booting789
- Programming Model806
- Pin Multiplexing810
- High Frequency Design815
- System Components822
  - Power Management Circuits822
  - Supervisory Circuits823
- Definition of Terms825
A Registers Reference827
- Overview828
  - Register Diagram Conventions828
  - Bit Types and Settings829
- System and Power Management Registers830
- ADSP-2146x External Port Registers844
- ADSP-2147x, ADSP-2148x External Port Registers871
- External Port DMA Control Registers (DMACx)886
- Peripheral Registers889
- DAI Signal Routing Unit Registers944
- Peripherals Routed Through the DAI976
- DPI Signal Routing Unit Registers1044
- Peripherals Routed Through the DPI1057
- Register Listing1099
B Peripheral Interrupt Control1133
- Interrupt Latency1133
- Interrupt Acknowledge1134
- Interrupt Completion1135
- Interrupt Priority1136
  - Peripherals with Multiple Interrupt Vector Addresses1139
  - Priority Interrupt Control Registers (PICRx)1140
C Audio Frame Formats1143
- Overview1144
- Standard Serial Mode1144
- I2S Mode1145
- Left-Justified Mode1147
- Right-Justified Mode1147
- TDM Mode1148
  - Packed I2S Mode1149
  - MOST Mode1150
- AES/EBU/SPDIF Formats1151
I Index1159
- Numerics1159
- A1159
- B1160
- C1161
- D1162
- E1165
- F1168
- G1170
- H1170
- I1170
- K1172
- L1173
- M1173
- N1175
- O1175
- P1176
- R1178
- S1180
- T1187
- U1189
- V1190
- W1190

Brand	Analog Devices
Model	SHARC ADSP-214 Series
Category	Computer Hardware
Language	English

Analog Devices SHARC ADSP-214 Series User Manual

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Analog Devices SHARC ADSP-214 Series Specifications

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