TCB Storage
2-18 ADSP-214xx SHARC Processor Hardware Reference
FFT Accelerator TCB
The FFT accelerator supports circular buffer chained DMA. Table 2-20
and Table 2-21 shows the required TCBs for chained DMA.
The input TCB controls both data and coefficients. Bit 20
(COEFFSEL) of the input chain pointer register (CPIFFT), indicates
whether the TCB is for loading data or coefficients. For coefficient
TCBs (COEFFSEL=1), circular buffering and the input length
(ILFFT) and base length (IBFFT) TCB fields are ignored.
Table 2-20. FFT Input TCBs
Address Register
CP[18:0] CPIFFT
CP[18:0] + 0x1 IBFFT
CP[18:0] + 0x2 ILFFT
CP[18:0] + 0x3 ICFFT
CP[18:0] + 0x4 IMFFT
CP[18:0] + 0x5 IIFFT
Table 2-21. FFT Output TCBs
Address Register
CP[18:0] CPOFFT
CP[18:0] + 0x1 OBFFT
CP[18:0] + 0x2 OLFFT
CP[18:0] + 0x3 OCFFT
CP[18:0] + 0x4 OMFFT
CP[18:0] + 0x5 OIFFT
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