FFT Accelerator
6-20 ADSP-214xx SHARC Processor Hardware Reference
Vertical FFT cycles
Data and coefficient reads: 2N × 2 + 2V × 2
Butterfly computes: (Vlog2V) × H
Data writes: 2N × 1
Special Prod cycles
Data and coefficient reads: 2N × 2 + 4N × 2
Product compute: 2 × 4N/4
Data writes: 2N × 1
Horizontal FFT cycles
Data and coefficient reads: 2N × 2 + 2H × 2
Butterfly compute: (Hlog2H) × V
Data writes: 2N × 1
Debug Features
The following sections describe the debugging features available on the
accelerator.
Local Memory Access
Setting the
FFT_DBG bit in the FFTCTL1 register puts the accelerator into
debug mode and allows all memory locations (coefficient and data mem-
ory) to be read and written indirectly, using FFTDADDR and FFTDDATA
registers. The MSB bits of the
FFTDADDR register determines if the access is
for the data or the coefficient memory.
Shadow Register
A shadow DMA status register, FFTSHDMASTAT, can read the DMA status
register without modifying the status values.
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