Peripheral Registers
A-102 ADSP-214xx SHARC Processor Hardware Reference
Channel Control Registers (MLB_CECRx)
These registers define the basic attributes of a given logical channel, such
as the channel enable, channel direction, and channel address. The defini-
tion of the bit fields in these registers vary by the selected channel type.
Figure A-48 and Table A-66 provide information for for asynchronous
and control channels and Figure A-49 and Table A-67 provide informa-
tion for for synchronous channels.
Figure A-48. MLB_CECRx Register (Asynch and Control Channels)
CA (7–0)
Channel Address
PCTH (12–8)
Packet Count Threshold,
I/O Mode
CE
Packet Count Enable
MDS (26–25)
Channel x Mode Select
CTYPE (29–28)
MASK (23–16)
Channel x Interrupt Mask
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
CTRAN
PCE
Channel x Enab le
Channel x Transmit Select
Channel x Type Select
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