ADSP-214xx SHARC Processor Hardware Reference 10-19
Serial Ports
Note that for I
2
S and left-justified mode, the MSTR bit allows programs to
select only the clock and frame sync to be simultaneously configured as
master or slave.
External Frame Sync Sampling
A variety of framing options are available on the SPORTs as shown in
Table 10-5.
When the SPORT is enabled, an already active externally applied
frame sync is not allowed to start operation. An additional feature
allows programs to configure the SPORTs to wait for a valid state
change from inactive to active for the external frame sync to con-
sider it valid. This is true for the first valid frame after the SPORT
is enabled and applicable to both level and edge sensitive frame
syncs. This feature is enabled by setting the frame sync edge detec-
tion bit (FSED, bit 2 in the SPCTLNx register).
Signals: Level Versus Edge Sampling
The SPORT slaves allow programs to sample the frame sync and data on
its signal level or edges depending on the operation mode. Note that in a
noise free environment it doesn’t matter which sampling type is selected.
In noisy environments however, the edge based sampling is prefered as it
allows better re-synchronization of the communication link.
Table 10-5. Framing Options
OPMODE External Frame Sync Sampling
Standard serial Level sensitive
Left-justified pair Edge detection
I
2
S
Edge detection
Packed Edge detection
Multichannel Level/edge sensitive
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