ADSP-214xx SHARC Processor Hardware Reference 15-21
Serial Peripheral Interface Ports
transfer occurs when the
RXS bit is set. This indicates that a new word has
been received and latched into the receive buffer, RXSPI. The RXS bit is set
shortly after the last sampling edge of SPICLK. There is a 4 PCLK cycle
latency for a master/slave device, depending on synchronization. This is
independent of the CPHASE and TIMOD bit settings and the baud rate.
Backward Compatibility
To maintain software compatibility with other SPI devices (68HC11), the
SPI transfer finished bit (SPIF) is also available for polling. This bit may
have slightly different behavior from that of other commercially available
devices. For a slave device, SPIF is set at the same time as RXS. For a master
device, SPIF is set one-half (0.5) of the SPICLK period after the last SPICLK
edge, regardless of CPHASE or CLKPL. The baud rate determines when the
SPIF bit is set. In general, SPIF is set after RXS, but at the lowest baud rate
settings (SPIBAUD < 4). The SPIF bit is set before the RXS bit, and conse-
quently before new data has been latched into the RXSPI buffer. Therefore,
for SPIBAUD = 2 or SPIBAUD = 3, the processor must wait for the RXS bit to
be set (after SPIF is set) before reading the RXSPI buffer. For larger SPI-
BAUD settings (SPIBAUD > 4), RXS is set before SPIF.
DMA Transfers
The SPI ports support both master and slave mode DMA. DMA is
enabled for
TIMOD bit = 10.
Enable the SPI port before enabling DMA.
For master mode, a DMA transfer starts after the DMA engine is enabled.
For slave mode the slave select pin (
SPI_DS_I) needs to be asserted to start
slave DMA operation.
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