ADSP-214xx SHARC Processor Hardware Reference 20-19
UART Port Controller
Error Interrupts
The UARTLSIE bit (bit 2 of the UARTIER register) enables interrupt genera-
tion on an independent interrupt channel when any of the following
conditions are raised by the respective bit in the UART line status register
(UARTLSR):
• Receive overrun error (UARTOE)
• Receive parity error (UARTPE)
• Receive framing error (UARTFE)
• Break interrupt (UARTBI)
In core transfers, the receive interrupt is generated for the following cases.
• When UARTRBR is full
• On a receive overrun error
• On a receive parity error
• On a receive framing error
• On a break interrupt (RXSIN held low)
• When UARTTHR is empty
• An address detect (
UARTADI) interrupt (for 9-bit mode)
• A transmit complete (
UARTTXFI) interrupt
The ISRs can evaluate the status bit field within the UART interrupt iden-
tification register (
UARTIIR) to determine the signalling interrupt source. If
more than one source is signalling, the status field displays the one with
the highest priority. Interrupts also must be assigned and unmasked by the
processor’s interrupt controller. The ISRs must clear the interrupt latches
explicitly.
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