SDRAM Controller (ADSP-2147x/ADSP-2148x)
3-20 ADSP-214xx SHARC Processor Hardware Reference
SDRAM Commands
This section provides a description of each of the commands that the SDC
uses to manage the SDRAM interface. These commands are handled auto-
matically by the SDC. A summary of the various commands used by the
on-chip controller for the SDRAM interface follows and is shown in
Table 3-5 on page 3-25.
• Load mode register—initializes the SDRAM operation parameters
during the power-up sequence.
• Single precharge—closes a specific internal bank depending on user
code.
• Precharge all—closes all internal banks, preceding any auto-refresh
command.
• Activate—activates a page in the required internal SDRAM bank
• Read/write
• Auto-refresh—causes the SDRAM to execute an internal CAS
before RAS refresh.
• Self-refresh entry—places the SDRAM in self-refresh mode, in
which the SDRAM powers down and controls its refresh opera-
tions internally.
• Self-refresh exit—exits from self-refresh mode by expecting
auto-refresh commands from SDC.
• NOP/command inhibit—no operation used to insert wait states
for activate and precharge cycles
Load Mode Register
This command is initializes SDRAM operation parameters. It is a part of
the SDRAM power-up sequence. Load mode register uses the address bus
of the SDRAM as data input. The power-up sequence is enabled by writ-
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