ADSP-214xx SHARC Processor Hardware Reference 10-49
Serial Ports
• In standard mode the
FS_BOTH bit (in the SPCTLx register) defines
the conditions of whether both channels are logically ANDed or
ORed.
• For all other operating modes, channels A and B are logically
ANDed. If both channels are enabled, both buffers need to be
updated by the DMA controller to drive data and frame sync
off-chip.
Note that for all operating modes, if the DIFS bit is set and the DMA
transfers have completed, the frame sync continues to drive off-chip and
the data output are zero with the DERRx bit set.
Interrupts
This section handles the various scenarios in which an interrupt is trig-
gered. Both the core and DMA are able to generate data interrupts for
receive or transmit operations. Moreover, the SPORT modules generate
error conditions which generate a separate interrupt.
Table 10-10 provides an overview of SPORT interrupts.
Table 10-10. SPORT Interrupt Overview
Interrupt Source Interrupt Condition Interrupt
Completion
Interrupt
Acknowledge
Default IVT
SPORT (standard,
I2S, left justified,
packed, multichan-
nel, 16 channels)
– DMA RX/TX done
– Core RX buffer full
– Core TX buffer empty
– DMA under/overflow
error
– Frame sync error
Internal transfer
or access comple-
tion
RTI instruction P3I–P8I,
P11I, P16I,
SPERRI
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