Analog Devices SHARC ADSP-214 Series User Manual

Operating Modes
12-10 ADSP-214xx SHARC Processor Hardware Reference
TDM Daisy Chain Mode
The SRCs are daisy chained together to achieve the TDM mode of
operation.
Figure 12-3. SRC Data Format
1/f
s
TDM MODE – 16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
SCLK
S DATA
LRCLK
SCLK
S DATA
LRCLK
SCLK
S DATA
I2S MODE – 16 BITS TO 24 BITS PER CHANNEL
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL
NOTES
1
LRCLK NORMALLY OPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY (f
S
).
2
3
PLEASE NOTE THAT 8 BITS OF EACH 32-BIT SUBFRAME ARE USED FOR TRANSMITTING
MATCHED-PHASE MODE DATA.
SCLK FREQUENCY IS NORMALLY 64
LRCLK EXCEPT FOR TDM MODE WHICH IS N 64 fS,
WHERE N = NUMBER OF STEREO CHANNELS IN THE TDM CHAIN.
LSBLSB
LEFT CHANNEL
RIGHT CHANNEL
MSB LSB
LSB
MSB
MSB
MSB
MSB LSB
LSB
MSB
MSB LSB
LSB
MSB
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
SCLK
S DATA
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Analog Devices SHARC ADSP-214 Series Specifications

General

Brand	Analog Devices
Model	SHARC ADSP-214 Series
Category	Computer Hardware
Language	English