Features
17-2 ADSP-214xx SHARC Processor Hardware Reference
Features
The following list describes the features of the shift register.
• 18-stage serial/parallel shift register
• 18-bit parallel data latch
• 18 parallel output signals (SR_LDO17-0) with can be three-stated
• Serial data input (
SR_SDI) and output pins (SR_SDO) allows cascad-
ing of multiple SR registers
• SRU routing unit allows the input selection for clock and data
from SPORT7-0, PCGA-B, DAI Pin buffer 8–1 or external SR pins
• Pin buffers remain three-stated coming out of reset until config-
ured by software as outputs
Access Type
Data Buffer Yes
Core Data Access N/A
DMA Data Access N/A
DMA Channels N/A
DMA Chaining N/A
Boot Capable N/A
Local Memory No
Clock Operation f
PCLK
/4
Table 17-1. Shift Register Specifications (Cont’d)
Feature Availability
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