ADSP-214xx SHARC Processor Hardware Reference 21-9
Two Wire Interface Controller
To better understand the mapping of TWI controller register contents to
a basic transfer, Figure 21-4 details the same transfer as above noting the
corresponding TWI controller bit names. In this illustration, the TWI
controller successfully transmits one byte of data. The slave has acknowl-
edged both address and data.
Bus Arbitration
The TWI controller initiates a master mode transmission (TWIMEN) only
when the bus is idle. If the bus is idle and two masters initiate a transfer,
arbitration for the bus begins. This is illustrated in Figure 21-5.
The TWI controller monitors the serial data bus (TWI_DATA) while the
TWI_CLOCK is high. If TWI_DATA is determined to be an active logic 0 level
while the internal TWI controller’s data is a logic 1 level, the TWI con-
troller has lost arbitration and ends generation of clock and data. Note
that arbitration is performed not only at serial clock edges, but also during
the entire time TWI_CLOCK is high.
Figure 21-3. Standard Data Transfer
Figure 21-4. Data Transfer With Bit Illustration
ACKR/W
ACK = ACKNOWLEDGE
S P8-BIT DATA ACK7-BIT ADDRESS
P = STOP
S = START
ACKMDIR
ACK = ACKNOWLEDGE
S PXMITDATA8[7:0] ACKMADDR[6:0]
P = STOP
S = START
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