Data Transfer
21-12 ADSP-214xx SHARC Processor Hardware Reference
Data Transfer
The TWI uses its transmit and receive buffers for data transfer (no DMA
capability). These buffers are described in the following sections.
Data Buffers
The TWI has two data buffer FIFOs, which are described in the following
sections.
8-Bit Transmit FIFO Register
The TWI 8-bit transmit FIFO register (TXTWI8) shown in Figure 21-7
holds an 8-bit data value written into the FIFO buffer. Transmit data is
entered into the corresponding transmit buffer in a first-in, first-out order.
Although peripheral bus writes are 32 bits, a write access to the TXTWI8
register adds only one transmit data byte to the FIFO buffer. With each
access, the transmit status (TWITXS) field in the TWIFIFOSTAT register is
updated. If an access is performed while the FIFO buffer is full, the core
waits until there is at least one byte space in the transmit FIFO buffer and
then completes the write access.
16-Bit Transmit FIFO Register
The TWI 16-bit FIFO transmit register (
TXTWI16) shown in Figure 21-8
holds a 16-bit data value written into the FIFO buffer. Although periph-
eral bus writes are 32 bits, a write access to the TXTWI16 register adds only
two transmit data bytes to the FIFO buffer. To reduce interrupt output
Figure 21-7. 8-Bit Transmit FIFO Register
XMTDATA8 (7–0)
Transmit FIFO 8-Bit
Data
09 837564 2114 12 11 101315
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