ADSP-214xx SHARC Processor Hardware Reference 17-1
17 SHIFT REGISTER –
ADSP-2147X
ADSP-2147x processors incorporate an 18 stage serial in, serial/parallel
out Shift Register (SR). The serial in–serial out mode can be used to delay
the serial data by a fixed amount of time. The serial output can also be
used to cascade the shift register modules on two or more processors. The
serial in–parallel out mode can be used to convert the serial data to paral-
lel. Table 17-1 lists the shift register specifications.
Table 17-1. Shift Register Specifications
Feature Availability
Connectivity
Multiplexed Pinout No
SRU DAI Required Yes
SRU DAI Default Routing Yes
SRU2 DPI Required No
SRU2 DPI Default Routing No
Interrupt Control N/A
Protocol
Master Capable N/A
Slave Capable N/A
Transmission Simplex N/A
Transmission Half Duplex N/A
Transmission Full Duplex N/A
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