TCB Storage
2-14 ADSP-214xx SHARC Processor Hardware Reference
Serial Port TCB
The serial ports support single and chained DMA. Table 2-14 shows the
required TCBs for chained DMA
SPI TCB
The serial peripheral interfaces supports both single and chained DMA.
However, unlike the serial ports, programs cannot insert a TCB in an
active chain. Table 2-15 shows the required TCBs for chained DMA.
Table 2-14. SPORT TCBs
Address Register
CP[27:0] CPSPx Chain Pointer
CP[27:0] + 0x1 ICSPx Internal Count
CP[27:0] + 0x2 IMSPx Internal Modifier
CP[27:0] + 0x3 IISPx Internal/External Index
Table 2-15. SPI/SPIB TCBs
Address Register
CP[18:0] CPSPI/B Chain Pointer
CP[18:0] + 0x1 ICSPI/B Internal Count
CP[18:0] + 0x2 IMSPI/B Internal Modifier
CP[18:0] + 0x3 IISPI/B Internal Index
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