ADSP-214xx SHARC Processor Hardware Reference 6-35
FFT/FIR/IIR Hardware Modules
1. The accelerator fetches four input data from the delay line and four
corresponding coefficients from the coefficient memory and feeds
them to the MAC units for multiply/accumulation.
2. The accelerator repeats the procedure with the next four input data
and coefficients until all the TAPs complete. For an N TAP filter
for example, this procedure is done N/4 times.
3. When all the TAPs complete, the accelerator adds the four MAC
outputs together to the previous partial sum (if any) to calculate
the final result.
4. Finally, that output sample is stored back in internal memory.
Internal Memory Storage
The following sections describe the storage format for the accelerator.
Coefficients and Input Buffer Storage
For any N TAP filter with coefficients:
C[i] i = 0,1,
…
N – 1
the coefficients should be stored in internal memory buffer in the order:
C[N – 1], C[N – 2]
…
C[1],C[0]
and the CI should point to C(N – 1)
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