SRU Programming
10-6 ADSP-214xx SHARC Processor Hardware Reference
SRU SPORT Receive Master
If the SPORT is operating as receive master, it must feed its master output
clock back to its input clock. This is required to trigger the SPORT’s state
machine. Using SPORT 4 as an example receive master, programs should
route SPORT4_CLK_O to SPORT4_CLK_I. This is not required if the SPORT is
operating as a transmitter in master mode.
SRU SPORT Signal Integrity
There is some sensitivity to noise on the clock (SPORTx_CLK) and frame
sync (SPORTx_FS) signals when the SPORT is configured as a master
receiver. By correctly programming the signal routing unit (SRU) clock
and frame sync registers, the reflection sensitivity in these signals can be
avoided.
Figure 9-9 on page 9-19 shows the default routing of the serial port where
the SRU maps to:
• The signal from the DAI pin (
DAI_PBxx_O) back to the SPORT
clock input (SPORTx_CLK_I)
• The SPORT clock output (
SPORTx_CLK_O) to the pin buffer input
(
DAI_PBxx_I)
SPORT7–0_CLK_PBEN_O Group F
SPORT7–0_FS_PBEN_O
SPORT7–0_DA_PBEN_O
SPORT7–0_DB_PBEN_O
SPORT7–0_TDV_PBEN_O
Table 10-3. SPORT DAI/SRU Signal Connections (Cont’d)
Internal Node DAI Connection SRU Register
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