Data Transfer
11-22 ADSP-214xx SHARC Processor Hardware Reference
ping-pong DMA, initialize the corresponding
IDP_DMA_IxA, IDP_DMA_IxB,
IDP_DMA_Mx and IDP_DMA_PCx registers.
DMA transfers for all 8 channels can be interrupted by changing the
IDP_DMA_EN bit in the IDP_CTL0 register. None of the other control settings
(except for the IDP_EN bit) should be changed. Clearing the IDP_DMA_EN
bit (= 0) does not affect the data in the FIFO, it only stops DMA transfers.
If the IDP remains enabled, an interrupted DMA can be resumed by
setting the IDP_DMA_EN bit again. But resetting the IDP_EN bit flushes the
data in the FIFO. If the bit is set again, the FIFO starts accepting new
data.
Programs can drop DMA requests from the FIFO if needed. If one chan-
nel has finished its DMA, and the global IDP_DMA_EN bit is still set (=1),
any data corresponding to that channel is ignored by the DMA machine.
This feature is provided to avoid stalling the DMA of other channels,
which are still in an active DMA state. To avoid data loss in the finished
channel, programs can clear (=0) IDP_DMA_EN bit as discussed in
previously.
Multichannel FIFO Status
The state of all eight DMA channels is reflected in the IDP_DMAx_STAT bits
(bits 24–17 of DAI_STAT register). These bits are set once the IDP_DMA_EN
and IDP_DMA_ENx bits are set, and remain set until the last data from that
channel is transferred. Even if
IDP_DMA_EN and IDP_DMA_ENx bits remain
set, the IDP_DMAx_STAT bits clear once the required number of data trans-
fers takes place.
Note that when a DMA channel is not used (that is, parameter reg-
isters are at their default values), the DMA channel’s corresponding
IDP_DMAx_STAT bit is cleared (= 0).
If the combined data rate from the channels is more than the DMA can
service, a FIFO overflow occurs. This condition is reflected for each chan-
nel by the individual overflow bits (
SRU_OVFx) in the DAI_STAT0 register.
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