ADSP-214xx SHARC Processor Hardware Reference 22-1
22 POWER MANAGEMENT
Power management is a vital tool that system designers can employ to
control internal and external clocking and maximize power savings.
Features
The following list describes the power management features.
• The PLL has various multiplier and divisor settings to generate a
flexible core clock.
• Allows changes to the output clock during runtime.
• RESETOUT pin can be used for boot handshake or as a debug aid.
• Resetting the PLL is possible without performing a new power-up
sequence.
• Power savings controls the shut-down of individual clocks to
peripherals.
Register Overview
Power Management Control Register (PMCTL). Governs the operation
of the PLL and configures and controls all PLL settings.
Power Management Control Register 1 (PMCTL1). This register con-
trols the peripheral’s clocks.
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