Functional Description
15-8 ADSP-214xx SHARC Processor Hardware Reference
connected to high, as it affects the functioning of certain bits in the
SPICTLx register.
Functional Description
Each SPI interface contain its own transmit shift (TXSR, TXSRB) and receive
shift (RXSR, RXSRB) registers (not user accessible). The TXSRx registers seri-
ally transmit data and the RXSRx registers receive data synchronously with
the SPI clock signal (SPICLK). Figure 15-1 shows a block diagram of the
SHARC processor SPI interface. The data is shifted into or out of the shift
registers on two separate pins: the master in slave out (MISO) pin and the
master out slave in (MOSI) pin.
During data transfers, one SPI device acts as the SPI master by controlling
the data flow. It does this by generating the SPICLK and asserting the SPI
device select signal (SPIDS). The SPI master receives data using the MISO
pin and transmits using the MOSI pin. The other SPI device acts as the SPI
slave by receiving new data from the master into its receive shift register
using the MOSI pin. It transmits requested data out of the transmit shift
register using the MISO pin.
Each SPI port contains a dedicated transmit data buffer (TXSPI, TXSPIB)
and a receive data buffer (RXSPI, RXSPIB). Transmitted data is written to
TXSPIx and then automatically transferred into the transmit shift register.
Once a full data word has been received in the receive shift register, the
data is automatically transferred into
RXSPIx, from which the data can be
read. When the processor is in SPI master mode, programmable flag pins
provide slave selection. These pins are connected to the
SPIDS of the slave
devices.
The SPI has a single DMA engine which can be configured to support
either an SPI transmit channel or a receive channel, but not both simulta-
neously. Therefore, when configured as a transmit channel, the received
data is essentially ignored. When configured as a receive channel, what is
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