ADSP-214xx SHARC Processor Hardware Reference 6-47
FFT/FIR/IIR Hardware Modules
an effect latency of two
PCLK cycles. Wait for at least four CCLK cycles after
selecting an accelerator before accessing any of its registers.
FIR Throughput
Accelerator input and output channels are used to connect to internal
memory. Data throughput is one 32-bit data word per peripheral clock
cycle for writes to memory, provided there are no conflicts. Read through-
put from memory, throughput is one 32-bit data word per two peripheral
clock cycles.
The following information describes the performance of the FIR accelera-
tor in processor cycles.
Total number of PCLK cycles for single rate filtering N<=1024 is:
(TCB load + 4 × N +W(N/4 + 2)) × C
and the total number of PCLK cycles for desimation is:
(TCB load + 4 × N + W(N/4 + 2) + (W – 1) × (M – 1) × 7) × C where:
• N – Number of taps
• W – Window size
• C – Number of channels
• TCB load = 49
PCLK cycles
• 4 × N – Number of cycles for loading coefficients an data consider-
ing two cycles for read
• N/4 + 2 – FIR compute cycles considering four pipelined MACs
• M – Decimation ratio
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