Functional Description
4-10 ADSP-214xx SHARC Processor Hardware Reference
Self-Synchronization
The link ports are designed to allow long distance connections to be made
between the driver and the receiver. This is possible because the links are
self-synchronizing—the clock and data are transmitted together. Only rel-
ative delay, not absolute delay between clock and data is relevant.
In addition, the LACKx signal inhibits transmission of the next word, not of
the current nibble or byte. For example, the current word is always
allowed to complete transmission. This allows delays of 3 cycles for the
LACKx signal to reach the transmitter.
Multi-Master Conflicts
Multi-master conflicts can be resolved using token passing. In token pass-
ing, the token is a software flag that passes between processors. At reset,
the token is set to reside in the link port of one device, making it the mas-
ter and the transmitter. When a receiver (slave) wants to become the
master, it may assert its LACKx line to get the master’s attention. The mas-
ter knows, through software protocol, whether it is supposed to respond
with actual data or whether it is being asked for the token. If the master
wishes to give up the token, it may send back a user-defined token release
word and thereafter clear its token flag. Simultaneously, the slave will set
its token and can thereafter transmit.
This example shown in Figure 4-7 is a typical case where the link port is
used as fast IO link. A FPGA bridge is required to communicate between
two different protocols. If using both link ports, full duplex operation is
possible without core intervention.
Figure 4-7. Fast I/O Link
PCI BUS
LINK PORT
BUS
NETWORK
CONTROLLER
FPGA
BRIDGE
ADSP-2146x
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