Analog Devices SHARC ADSP-214 Series - Page 273

ADSP-214xx SHARC Processor Hardware Reference 4-9
Link Ports—ADSP-2146x
Figure 4-5. Relationship Between ACK and LCLK
Figure 4-6. Relationship Between Internal LCLK and LCLK at Pads
LACKx
DRIVEN BY
RECEIVER
BYTE 1
BYTE 2
LCLKx STAYS HIGH IF LA
SAMPLED LOW ON PREV
LCLKx FALLING EDGE
LDAT7
- 0
DRIVEN BY
TRANSMITTER
LCLKx
DRIVEN BY
TRANSMITTER
TRANSMITTER SAMPLES LACKx
HERE TO DECIDE WHETHER TO
TRANSMIT NEXT WORD
BYTE 3
(MSB)
BYTE 0
(LSB)
LACKx MAY
DEASSERT AFTER
BYTE 0
TRANSMIT DATA FOR NEXT WORD
HELD UNTIL LACKx IS ASSERTED
LACKx
DRIVEN BY
RECEIVER
LCLKx HELD HIGH
UNTIL LACKx
GOES HIGH
INTERNAL
LINKCLK
IN TRANSMITTER
LACKx MAY
DEASSERT AFTER
BYTE 0
START OF FIRST
BYTE TRANSMISSION
LCLKx
DRIVEN BY
TRANSMITTER
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