ADSP-214xx SHARC Processor Hardware Reference 6-65
FFT/FIR/IIR Hardware Modules
Channels Complete Interrupt – This interrupt is generated when all the
channels are complete or when one iteration of time slots completes.
MAC Status Interrupt – The status interrupt sources are derived from the
FIRMACSTAT register. For more information, see “IIR MAC Status Register
(IIRMACSTAT)” on page A-91.
Service Channel Interrupts – Based on the IIR_CCINTR bit in the IIRCTL1
register, both bits (IIR_DMAWCDONE or IIR_DMAACDONE) are set in the
IIRDMSTAT register if either of the conditions is met. The interrupt service
routine should read (to clear) both bits.
Service MAC Status Interrupts – A MAC status interrupt is generated
whenever a floating-point operation results in an arithmetic exception.
Reading the IIRMACSTAT register returns for which MAC unit is causing an
exception.
Debug Features
The following sections describe the debugging features available on the
accelerator.
Local Memory Access
The contents of IIR delay line and coefficient memories are made observ-
able for debug by setting the
IIR_DBGMODE/IIR_DBGMEM and IIR_HLD bits in
the
IIRDEBUGCTL control register. The debug address register (IIRDBGADDR)
and four data registers are provided for debug operations. Bit 11 of the
this register selects coefficient memory if set (=1) and selects delay line
memory in cleared (=0).
The 40-bit wide debug mode read data register is organized as:
• The
IIRDBGRDDATA_L register holds the lower 32 bits
• The
IIRDBGRDDATA_H register holds the upper 8 bits
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