ADSP-214xx SHARC Processor Hardware Reference 5-3
Memory-to-Memory Port DMA
Functional Description
The MTM module owns two DMA channels one for read and one for
write including a data buffer which stores up to 2x32-bit data. After the
DMA is configured, the read DMA channel fills the buffer with 64-bit
data. After this transfer, the write DMA channel becomes active and emp-
ties the buffer according to its destination. This procedure is repeated
until the DMA count is zero.
The memory-to-memory DMA controller is capable of transferring 64-bit
bursts of data between internal memories.
The MTM controller supports data in normal word address space
only (32-bit). External to external DMA transfers are not
supported.
Data Transfer Types
The memory-to-memory DMA controller is capable of transferring 64-bit
bursts of data between internal memories.
Data Buffer
The MTMFLUSH bit in the MTMCTL register can be set to flush the FIFO and
reset the read/write pointers. Setting and resetting the
MTMDEN bit only
starts and stops the DMA transfer, so it is always better to flush the FIFO
along with
MTMDEN reset.
Note that the MTMFLUSH bit should not be set along with the MTMDEN bit set.
Otherwise the FIFO is continuously flushed leading to DMA data
corruption.
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