ADSP-214xx SHARC Processor Hardware Reference 23-27
System Design
This overrides the kernel with the application’s IVT. However, the
application needs to temporarily include the RTI instruction at the
peripheral interrupt address, allowing a return from interrupt.
Moreover, the last instruction in the final routine is a jump (db)
including an IDLE.
3. The RTI instruction overrides the IVT address where user code is
stored.
While both DMA types (“Loading the Boot Kernel Using DMA”
and “Loading the Application’s Interrupt Vector Table”) seem sim-
ilar, loading the kernel is accomplished using hardware while
loading the IVT is accomplished using software.
It is very important to match the dedicated kernel to the dedicated
boot type (for example SPI kernel and SPI boot type) in the elf-
loader property page. If this is not done, the RTI instruction (in
“Loading the Application’s Interrupt Vector Table”) will not be
placed at the correct address. This causes execution errors.
Starting Program Execution
The processed interrupt returns the sequencer to the reset location by per-
forming the two following steps.
1. Overriding the RTI instruction with user code.
2. Starting program execution from the reset location.
For other details relating to processor booting, see the boot loader source
files that ship with the VisualDSP tools.
Memory Aliasing in Internal Memory
The boot loader takes advantage of memory aliasing which is essential to
understand the boot mechanisms. For information on memory aliasing,
see the SHARC Processor Programming Reference, “Memory” chapter.
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