ADSP-214xx SHARC Processor Hardware Reference A-87
Registers Reference
IIR Accelerator Registers
The following sections describe the registers used to program and debug
the FIR accelerator.
IIR Global Control Register (IIRCTL1)
The
IIRCTL1 register, shown in Figure A-40 and described in Table A-52,
is used to configure the global parameters for the accelerator. These
include number of channels, channel auto iterate, DMA enable, and accel-
erator enable.
Table A-51. FIRDEBUGCTL Register Bit Descriptions (RW)
Bits Name
0 FIR_DBGMODE Debug Mode Enable.
0 = Disable
1 = Enable
For local memory access, the FIRCTL1 register can be cleared.
1FIR_HLD Hold Or Single Step. The function of this bit is based on the
FIR_DBGMEM bit setting.
For FIR_DBGMEM = 0:
1 = Single step
for FIR_DBGMEM = 1:
1 = Hold data
2 (WO) FIR_RUN Release MAC. This bit is self clearing after one FIR clock cycle.
3Reserved
4 FIR_DBGMEM Local Memory Access. If set, the data and coefficients memory
can be indirectly accessed.
5 FIR_ADRINC Address Auto Increment. If this bit is set, the address register
auto increments on DBGMEMWRDAT write and DBG-
MEMRDDAT reads.
31–6 Reserved
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