Interrupts
9-38 ADSP-214xx SHARC Processor Hardware Reference
Enabling responses to changes in conditions of signals (including changes
in DMA state, introduction of error conditions, and so on) can only be
done using the
DAI_IMASK_RE register.
DAI Interrupt Acknowledge
Any asynchronous or synchronous interrupt causes a latency, since it
forces the core to stop processing an instruction in process, then vector to
the interrupt service routine (ISR), (which is basically an interrupt vector
table (IVT) lookup), then proceed to implement the instruction refer-
enced in the IVT. For more information, see “Peripheral Interrupt
Control” in Appendix B, Peripheral Interrupt Control.
When an interrupt from the DAI must be serviced, one of the two core
ISRs must query the DAI’s interrupt controller to determine the source(s).
Sources can be any one or more of the interrupt controller’s 32
configurable channels (DAI_INT31-0). For more information, see “Inter-
rupt Controller Registers” on page A-149.
The DAI triggers two interrupts in the primary IVT—one each for
low or high priority. When any interrupt from the DAI needs to be
serviced, one of the two core ISRs must interrogate the DAI’s inter-
rupt controller to determine the source(s).
When a DAI interrupt occurs, the high or low priority core ISR queries its
corresponding register to determine which of the 32 interrupt sources
requires service. Sources can be any one or more of the interrupt control-
ler’s 32 configurable channels. When DAI_IMASK_H is read, the high
priority latched interrupts are cleared. When
DAI_IMASK_L is read, the low
priority latched interrupts are cleared.
Reading the DAI’s interrupt latches clears the interrupts
(Read-to-Clear bit type). Therefore, the ISR must service all the
interrupt sources it discovers. That is, if multiple interrupts are
To Next Page
Loading...
Need help?
General
