Analog Devices SHARC ADSP-214 Series - Clocking AMI;SDRAM

ADSP-214xx SHARC Processor Hardware Reference 3-5
External Port
DDR2 Refresh Control Register (DDR2RRC). The DDR2 refresh rate
control register provides a programmable refresh counter which has a
period based value which coordinates the supplied clock rate with the
DDR2 device's required refresh rate.
DDR2 DLL Control Registers (DLL1-0CTL1). A built-in DLL in the
DDR2 controller provides a 90º phase shifted clock to manage the data
(DDR2_DATA) to data strobe (DDR2_DQS) timing relationships. For
each data byte a control register is responsible. The bits are used to reset
the DLL logic and to start a new DLL initialization.
DDR2 DLL Status Registers (DLL1-0STAT0). After the built-in DLL
has started the bits return the status if the DLL has locked. A control reg-
ister is responsible for each data byte.
DDR2 Pad Control Registers (DDR2PADCTL1–0). If the DDR2 inter-
face is not used, these registers should be used to power-down the receiver
pads for further power savings.
Clocking AMI/SDRAM
The fundamental timing clock of the external port is SDRAM clock
(SDCLK).
The AMI/SDRAM controller is capable of running at up to 166 MHz and
0can run at various frequencies, depending on the programmed SDRAM
clock (
SDCLK) to core clock (CCLK) ratios. The various possible
AMI/SDRAM clock to core clock frequency ratios are shown in
Table 3-2.
For more information on clock settings refer to TBD IN PWR MGMT.
For information processor instruction rates, see the appropriate processor
data sheets.
www.BDTIC.com/ADI