Data Transfer
3-84 ADSP-214xx SHARC Processor Hardware Reference
Data Transfer
The AMI can access data from both the core and through DMA. The fol-
lowing sections describe these options.
Data Buffers
The asynchronous memory interface has two 1 deep data buffers, one each
for the transmit and receive operations. These are described in the sections
that follow.
AMI Receive Buffer
Reads from external memory are done through the 1 deep receive packing
buffer (AMIRX). When an external address that is mapped to the AMI in
the EPCTL register is accessed, it receives 8/16-bit data and packs the data
based on the packing and control modes in the AMI control register
(AMICTLx). Once a full packed word is received, the internal status signal is
deasserted and new reads are allowed.
The AMI provides the interface to the external data pins as well as to the
processor core or to the internal DMA controller. When the AMI receives
data, it is passed by internal hardware to the DMA controller or to the
external port control bus, depending on which entity requested the data.
AMI Transmit Buffer
Writes to external memory are done through the 1 deep transmit packing
buffer (
AMITX). When an external address that is mapped to the AMI in
the
EPCTL register is accessed, it receives data from internal memory using
the DMA controller or through direct core writes.
Once a full word is transferred out of the AMI, the internal status signal is
deasserted and new writes are allowed. No more external transfers can start
while the AMI module is not empty.
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