ADSP-214xx SHARC Processor Hardware Reference 3-57
External Port
Self-Refresh Entry
Self-refresh mode causes refresh operations to be performed internally by
the DDR2 controller, without any external control. This means that the
controller does not generate any auto refresh cycles while it is in
self-refresh mode. The self-refresh entry command is performed by writ-
ing a 1 to the DDR2SRF bit of the memory control register (DDR2CTL0). This
deasserts the DDR2_CKE pin to put the device into self-refresh mode. In this
mode, the DDR2 on-chip DLL is put into reset in order to reduce power
consumption.
If any of the two DDR2 clocks is not required in a system during
self-refresh, they can be stopped by setting the DIS_DDR2CTL bit in the
DDR2CTL0 control register. This reduces the power consumption in a sys-
tem and is shown in the following code example.
ustat1 = dm(DDR2CTL0);
bit set ustat1 DDR2SRF; /* enter self-refresh */
dm(DDR2CTL0) = ustat1;
nop;
ustat2 = dm(DDR2STAT0);
bit tst ustat2 DDR2SRA; /* test self-refresh entry */
if not TF jump (pc,—2);
ustat1 = dm(DDR2CTL0);
bit set ustat1 DIS_DDR2CTL; /* freeze DDR2 clock */
dm(DDR2CTL0) = ustat1;
nop;
This requires careful software control because the DIS_DDR2CTL bit
is cleared during runtime. Systems may become unstable if this bit
is cleared too early because the system can lose control of the
DDR2 memory device.
Self-Refresh Exit
The DDR2 remains in self-refresh mode for at least t
RAS
and until an
internal access to DDR2 space occurs. When exiting from self-refresh
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