Peripherals Routed Through the DAI
A-202 ADSP-214xx SHARC Processor Hardware Reference
Transmit Status Bit Registers for Subframe A/B
(DITCHANAx/Bx)
These registers provide status information for transmitter subframe A and
B. The first five bytes of the channel status may be written all at once to
the control registers for both A and B channels. As the data is serialized
and transmitted, the appropriate bit is inserted into the channel status area
of the 192-word frame. Note that these registers are used in standalone
mode only.
There are six channel status registers associated with subframe A (left
channel) and six user bits buffer registers associated with subframe B
(right channel). Since a block owns 2 x 192 frames, 24 bytes per frame are
required for storage. Note that status byte 0 is available in the DITCTL reg-
ister. These registers are listed with their locations in Table A-105 and
Table A-106.
Table A-105. DITCHANAx Registers (RW)
Register Bits 7–0 Bits 15–8 Bits 23–16 Bits 31–24
DITCTL BYTE0
DITCHANA0 BYTE1 BYTE2 BYTE3 BYTE4
DITCHANA1 BYTE5 BYTE6 BYTE7 BYTE8
DITCHANA2 BYTE9 BYTE10BYTE11BYTE12
DITCHANA3 BYTE13 BYTE14 BYTE15 BYTE16
DITCHANA4 BYTE17 BYTE18 BYTE19 BYTE20
DITCHANA5 BYTE21 BYTE22 BYTE23 Reserved
Table A-106. DITCHANBx Registers (RW)
Register Bits 7–0 Bits 15–8 Bits 23–16 Bits 31–24
DITCTL BYTE0
DITCHANB0 BYTE1 BYTE2 BYTE3 BYTE4
DITCHANB1 BYTE5 BYTE6 BYTE7 BYTE8
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