Processor Booting
23-8 ADSP-214xx SHARC Processor Hardware Reference
Boot Mechanisms
In order to ensure proper device booting, the following hardware mecha-
nisms are available on the processor.
• Peripheral boot configuration pins (BOOT_CFGx) configure which
peripheral boot stream is activated after power-up.
• Peripheral control and DMA parameter settings define the DMA
channel which is started after RESETOUT is asserted based on the
boot configuration pins.
• Peripheral interrupt is enabled after reset for the boot peripheral.
• During kernel load the core is put in IDLE. After the interrupt is
generated the core jumps to reset location and starts kernel
execution.
External Port Booting
The ADSP-214xx processors allow booting through the external port. The
boot setting is configured through the BOOTCFG2–0 pins.
The asynchronous memory interface (AMI) supports an 8-bit user boot
called AMI boot. Only the MS1 signal is used for AMI (FLASH/EEPROM)
booting. Table 23-2 shows the bit settings for AMI boot. These bits are
described in detail in “AMI Control Registers (AMICTLx)” on page A-21.
After RESETOUT deasserted, the processor starts to drive:
•
ADDR23–0
• Chip select MS1 to the EPROM/FLASH
• AMI_RD strobe with 23 SDCLK cycle wait states
• Read input data 7–0
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