Functional Description
14-8 ADSP-214xx SHARC Processor Hardware Reference
Divider Mode Selection
If frame sync divisor > 1 the PCG frame sync output frequency is equal to
the input clock frequency, divided by a 20-bit integer. This integer is
specified in the
FSDIV bit field (bits 19–0 of the PCG_CTLx0 register).
However if the frame sync divisor is zero or one, the PCG’s frame sync
clock generation unit is bypassed, and the frame sync input is connected
directly to the frame sync output. For FSDIV=0, 1 the PCG_PWx registers
have different functionality than in normal mode.
Phase Shift
Phase shift is a frame sync parameter that defines the phase shift of the
frame sync with respect to the input clock of the same unit. This feature
allows shifting of the frame sync signal in time relative to the clock input
signal. Frame sync phase shifting is often required by peripherals that need
a frame sync signal to lead or lag a clock signal.
For example, the I
2
S protocol specifies that the frame sync transition from
high to low occur one clock cycle before the beginning of a frame. Since
an I
2
S frame is 64 clock cycles long, delaying the frame sync by 63 cycles
produces the required framing.
Phase shifting is represented as a full 20-bit value so that even when the
frame sync is divided by the maximum amount, the phase can be shifted
to the full range, from zero to one input clock short of the period.
Phase shifting is specified as a 2 x 10-bit divider value in the
FSxPHASE_HI bit field (bits 29–20) of the PCG_CTLxO register and in
the FSxPHASE_LO bit field (bits 29–20) of the PCG_CTLx1 register.
A single 20-bit value spans these two bit fields. The upper half of the word
(bits 19–10) is in the PCG_CTLxO register, and the lower half (bits 9–0) is in
the PCG_CTLx1 register.
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