Peripherals Routed Through the DAI
A-204 ADSP-214xx SHARC Processor Hardware Reference
User Bit Update Register (DITUSRUPD)
This register is a 1-bit wide register (WO). After writing to the user bits
registers (DITURSBITAx and DITUSRBITBx), a value of 0x1 must be written
into DITUSRUPD register to enable the use of these bits in the next block of
transfer.
Receiver Registers
The following sections describe the receiver registers.
Receive Control Register (DIRCTL)
This 32-bit register, described in Table A-109 is used to set up error con-
trol and single-channel double-frequency mode.
Table A-108. DITUSRBITBx Registers (RW)
Register Bits 7–0 Bits 15–8 Bits 23–16 Bits 31–24
DITUSRBITB0 BYTE0 BYTE1 BYTE2 BYTE3
DITUSRBITB1 BYTE4 BYTE5 BYTE6 BYTE7
DITUSRBITB2 BYTE8 BYTE9 BYTE10 BYTE11
DITUSRBITB3 BYTE12 BYTE13 BYTE14 BYTE15
DITUSRBITB4 BYTE16 BYTE17 BYTE18 BYTE19
DITUSRBITB5 BYTE20 BYTE21 BYTE22 BYTE23
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