ADSP-214xx SHARC Processor Hardware Reference A-117
Registers Reference
Period (WDTCNT)
The
WDTCNT register, shown in Table 3, holds the 32-bit unsigned count
value. The WDTCNT register must always be accessed with 32-bit
read/writes.
The watchdog count register holds the programmable count value. A valid
write to the watchdog count register also preloads the watchdog current
counter. For added safety, the watchdog count register can only be
updated when the WDT is disabled and WDT configuration space is
unlocked by programming the command in the WDTUNLOCK register.
Unlock (WDTUNLOCK)
The WDTUNLOCK register protects the WDT configuration space against
accidental writes from the processor core. Before attempting to write to
the WDT configuration space, the core must unlock the WDT by writing
the command value (0xAD21AD21) to this register. Attempts by the core
to write to WDT configuration space without this command causes the
WDT to expire. This exception is captured in the
WDTSTATUS register.
After configuring the WDT configuration space, the core needs to lock it
again by writing any value other than the command value to the
WDTUN-
LOCK
register.
1OSCPWRDWNInternal RC Oscillator Power Down.
0 = Oscillator is powered up
1 = Oscillator is powered down
2OSCRST Internal RC Oscillator Reset.
0 = Oscillator is reset
1 = Oscillator out of reset
Table A-74. WDTCLKSEL Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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