Interrupts
13-20 ADSP-214xx SHARC Processor Hardware Reference
Receiver Interrupts
The following three receiver status bits (DAI_IRPTL_x) generate an
interrupt.
• No audio (DIR_NOAUDIO_INT)
• Emphasized audio (
DIR_EMPHASIS_INT)
• Status change (
DIR_STATCNG_INT)
Note the Status change interrupt is generated if any of the 40 status bits
(bytes 4–0) have changed.
Receiver Error Interrupts
The following five receiver error status bits (DAI_IRPTL_x) generate an
interrupt.
• Receiver Locked (DIR_LOCK_INT)
• Validity (DIR_VALID_INT)
• No Audio Stream (DIR_NOSTREAM_INT)
• CRC Error (DIR_CRCERROR_INT)
• Parity or biphase Error (
DIR_ERROR_INT)
Notice that parity error and biphase error are ORed together to form a
DIR_ERROR_INT interrupt. The CRCCERROR bit is not available in DIRSTAT
register. The CRCCERROR interrupt latch bit is set whenever the CRCC
check of the channel status bits fails. The CRCC check is only performed
if channel status bit 0 of byte 0 is high, indicating professional mode.
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