Interrupts
8-14 ADSP-214xx SHARC Processor Hardware Reference
Interrupts
The buffer start and buffer done interrupts (bit 19 and bit 18 respectively)
can unmasked in the channel control registers (MLB_CECRx) to indicate the
start and end of a DMA. The MLB interrupt is not selected as one of the
19 programmable interrupts by default. To use the MLB interrupt as one
of the 19 programmable interrupts, the appropriate 5 bits in the PICRx
register have to be programmed to 0x1D. For example, to use MLB inter-
rupt as P18I, the PICR3 register needs to be programmed to 0x1D.
Table 8-2 provides an overview of MLB interrupts.
Table 8-2. Overview of MLB Interrupts
Interrupt
Source
Interrupt Condition Interrupt
Completion
Interrupt
Acknowledge
Default IVT
MLB
(31channels)
System Status Interrupts
-System Detects Channel Scan
-Network Unlock
-Network Lock
-Reset Command
-Subcommand
-MLB Lock
-MLB Unlock
-System Service Request
Enable
At event detec-
tion
-Write 1 to corre-
sponding bit in
MLB_SSCR register
to clear except for
SSRE bit which is
cleared by hardware.
- RTI instruction
Route MLBI
(PICRx) to any
PxxI
Channel Status Interrupts
-Receive Service Request -Buf-
fer Done
-Transmit Service Request
-Buffer Start
-Buffer Error
-Protocol Error
-Detect Break (control and
asynchronous only)
-Lost Frame Synchronization
(synchronous only)
Write 0x0000FFFF to
MLB_CSCRx regis-
ter. This clears corre-
sponding interrupt bit
in MLB_CICR regis-
ter
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