ADSP-214xx SHARC Processor Hardware Reference 3-25
External Port
Address Mapping
To access SDRAM, the controller multiplexes the internal 32-bit
non-multiplexed address into three portions:
• Row address bits
• Column address bits
• Bank address bits
The non multiplexed address that is seen from the core/DMA is referred
to as IA31–0 in the following sections.
Table 3-5. SDRAM Pin States During SDC Commands
Command SDCKE
(n–1)
SDCKE
(n)
MS3–0 SDRAS SDCAS SDWE SDA10 Addresses
Mode
register set
1 1 0 0 0 0 Opcode Opcode
Activate 1 1 0 0 1 0 Valid Valid
Read 1 1 0 1 0 1 0 Valid
Single
Precharge
1 1 00100 Valid
Precharge all1 1 00101 X
Write 1 1 01000 Valid
Auto-refresh1 1 0001X X
Self-refresh
entry
1 0 0001X X
Self-refresh0 0 XXXXX X
Self-refresh
exit
0 1 1XXXX X
Nop 1 1 0111X X
Inhibit 1 1 1XXXX X
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