ADSP-214xx SHARC Processor Hardware Reference 23-19
System Design
16-Bit SPI Packing
Figure 23-7 shows how a 16-bit SPI host packs 48-bit instructions at PM
addresses PMaddr0 and PMaddr1. For 16-bit hosts, two 16-bit words are
packed into the shift register to generate a 32-bit word. The 32-bit word
shifts to internal program memory during the kernel load.
The following code shows a 48-bit instruction executed:
[PMaddr0] 0x112233445566
[PMaddr1] 0x7788AABBCCDD
The 16-bit SPI host packs or prearranges the data as:
The initial boot of the 256-word loader kernel requires a 16-bit host to
transmit 768 16-bit words. Two packed 16-bit words comprise the 32-bit
word. The SPI DMA count value of 0x180 is equivalent to 384 words.
Therefore, the total number of 16-bit words loaded is 768.
Figure 23-7. 16-Bit SPI Master/Slave Packing
SPI word 1 = 0x5566
SPI word 2 = 0x3344
SPI word 3 = 0x1122
SPI word 4 = 0xCCDD
SPI word 5 = 0xAABB
SPI word 6 = 0x7788
SPI_MOSI_I/SPI_MISO_I
16-bit
Word N
RXSPI
Internal
Memory
32 32
32
16-bit
Word N
DMA
RXSR
To Next Page
Loading...
