Interrupts
4-16 ADSP-214xx SHARC Processor Hardware Reference
DMA Transfers
Each link port supports a DMA channel.
Note that the link ports do not support internal to internal mem-
ory transfers like previous SHARCs (no link assignment register).
If internal to internal memory transfers are required, refer to
“External Port DMA” on page 3-65.
In standard DMA operations, the software needs to set up the DMA
parameter registers before the link port control register is configured.
After setting the DMA enable bit the transfer starts until the word count
reaches zero, the DMA has finished.
Interrupts
The following sections and Table 4-2 provide details on using link port
interrupts.
Table 4-2. Link Port Interrupt Overview
Interrupt
Source
Interrupt Condition Interrupt
Completion
Interrupt
Acknowledge
Default IVT
Link port
Core
DMA
–DMA RX/TX done
–core RX buffer full
–core TX buffer empty
–link service request
–invalid transmit
attempt
–internal transfer
completion
–access completion
RTI instruction Need to route
LPxI (PICRx) to
any PxxI
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