ADSP-214xx SHARC Processor Hardware Reference 23-1
23 SYSTEM DESIGN
This chapter discusses different processor reset methods, boot modes and
pin multiplexing. In addition, information about high speed design is
illustrated with some examples of supervisor circuits used in conjunction
with the SHARC processor. These topics are located in the following
sections.
• “Processor Reset” on page 23-3
• “Processor Booting” on page 23-7
• “Pin Multiplexing” on page 23-28
• “High Frequency Design” on page 23-33
• “System Components” on page 23-40
Before proceeding with this chapter it is recommended that you
become familiar with the SHARC core architecture. This informa-
tion is presented in the SHARC Processor Programming Reference.
Features
The following list describes the features for reset and multiplexing.
• Five reset options: hardware, software, emulation, running reset
and watchdog reset.
• Different master or slave boot mechanisms.
• Hardware and software reset for processor booting.
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