ADSP-214xx SHARC Processor Hardware Reference 6-19
FFT/FIR/IIR Hardware Modules
status interrupt occurs programs can find the cause of the interrupt by
polling the MAC status register. The MAC status bits causing the inter-
rupt are sticky and cleared when the MAC status register is read. For more
information, see “Multiplier Status Register (FFTMACSTAT)” on
page A-78.
FFT Performance
In this section:
V = Number of rows
H = Number of columns
N = V × H
• Reads from internal memory take 2 cycles/word.
• Writes to internal memory take 1 cycle/word.
• It takes 2 PCLK cycles to compute a single complex butterfly by the
FFT computation.
For performance consideration each FFT computation is accompanied
with a preceding Read DMA and a post write DMA.
Small FFT (N is <= 256)
Data reads: 2N × 2
Butterfly computes: N log2N cycles (A radix2 takes N/2 log2N x 2
PCLK
cycles)
Data write: 2N × 1
Large FFT (N >= 256)
Total number of performance cycles = (Vertical FFT + Special Prod +
Horizontal FFT) cycles.
To Next Page
Loading...
Need help?
General
