System and Power Management Registers
A-12 ADSP-214xx SHARC Processor Hardware Reference
ADSP-2147x/ADSP-2148x Power Management
Registers
The registers described in the following sections are specific to the
ADSP-2147x and ADSP-2148x processors.
Power Management Control Registers (PMCTL)
The following sections describe the registers associated with the processors
power management functions.
The power management control register, shown in Figure A-4, is a 32-bit
memory-mapped register. This register contains bits to control phase lock
loop (PLL) multiplier and divider (both input and output) values, PLL
bypass mode, and clock enabling control for peripherals (see Table A-5).
This register also contains status bits, which keep track of the status of the
CLK_CFG pins (read-only). The reset value of PMCTL is dependent on the
CLK_CFG pins (bits 5–0 and 17–16).
16 ACCOFF Shutdown Clock to Accelerator.
0 = Accelerator is in normal mode
1 = Shutdown clock to accelerator
18–17 ACCSEL Accelerator Select.
00 = Select FIR
01 = Select IIR
10 = Select FFT
11 = Reserved
19 MLBOFF Shutdown Clock to Media Local Bus.
0 = MLB is in normal mode
1 = Shutdown clock to MLB
31–20 Reserved
Table A-4. PMCTL1 Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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