ADSP-214xx SHARC Processor Hardware Reference 3-129
External Port
3. Execute the desired PLL programming sequence. (For more infor-
mation, see “PLL Start-Up” on page 22-9.)
4. Wait 4096
CLKIN cycles (RESETOUT asserted) which indicates the
PLL has settled to the new frequency.
5. Reprogram the SDRAM registers (SDRRC, SDCTL) with values appro-
priate to the new SDCLK frequency and assure that the SDPSS bit is
set.
6. Bring the SDRAM out of self-refresh mode by performing a
dummy read SDRAM access.
7. The SDC now issues the commands PREA, 8xREF and MRS to initial-
ize the SDC and the SDRAM to the new frequency.
The SDRAM device is now ready to be accessed.
DDR2 Controller
The following sections are specific to DDR2 SDRAM memory on the
ADSP-2146x processor.
Power-Up Sequence
The following steps are used to power-up the DDR2 device.
1. Ensure the minimum DDR2 clock frequency is stable and at least
125 MHz (according to datasheet).
2. Program the core to DDR2 clock ratio using the
PMCTL register. For
PLL changes wait at least 4096 core cycles, for output divider
changes at least 15 core clock cycles for effect latency.
3. If a new frequency is desired, put the on-chip DLL into reset using
DLL1-0CTL1 registers.
4. Wait at least 9 core cycles for the DLL to lock to a new frequency.
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